FHM3695 DC/DC Adjustable Buck Power Module ( 4V-16V Input, 0.6V-5.5V Output )

Features

Input Voltage Range： 4V-16V

Output Voltage： 0.6-5.5V adjustable

Maximum Efficiency： 95%

Rated Output Current： 20A

Maximum Output Current： 25A

Multiphase Parallel Operation: Up to 8 phases can be paralleled, with a maximum paralleled current up to 200A.

Dimensions:  10mm × 12mm ×4.32mm（LGA）

Applications

Telecommunications and Networking Systems

Industrial Equipment

Servers and Computing Systems

FPGA/ASIC for AI and Data Mining

Description

FHM 3695-25 is an expandable, fully integrated, plastic-encapsulated power module with a PMBus interface. FHM 3695-25 offers a complete power supply solution capable of delivering a maximum output current of up to 25A, with excellent load regulation and line regulation. It operates efficiently over a wide load range and can be paralleled to provide higher load currents.

FHM 3695-25 utilizes Multiphase Constant On-Time (MCOT) control, which provides ultra-fast transient response and simple loop compensation. The PMBus interface offers configuration of the module and monitoring of critical parameters.

FHM 3695-25 features comprehensive protection functions, including Over-Current Protection (OCP), Over-Voltage Protection (OVP), Under-Voltage Protection (UVP), and Over-Temperature Protection (OTP). FHM 3695-25 minimizes the use of external components and adopts an LGA-59 (10mm×12mm×4.32mm) package.

Typical Applications

PIN CONFIGURATION

TOP VIEW

Electrical Characteristics

Note :

 Stresses above the values listed in the "Limit Values" section may cause permanent damage to the device. Prolonged exposure to any of the absolute maximum ratings may affect the reliability and lifespan of the device.

Operation 

The FHM 3695-25 is a fully integrated power solution that comes in a 10×12×4.32mm LGA package, providing a rated output current of 20A and a peak output current of up to 25A. For applications requiring currents exceeding 25A, parallel connection can be utilized to provide higher output currents.

The FHM 3695-25 employs a Constant On-Time (COT) control method, resulting in fast transient response. Internal slope compensation ensures stable operation in applications using zero ESR ceramic output capacitors.

Multiphase Operation

In a multiphase configuration, one master phase and up to seven slave phases are connected in parallel. All phases equally distribute the output current. A typical application circuit exemplifies the parallel configuration of two FHM 3695-25 devices. In a multiphase setup, the TAKE pin of the master phase needs to be pulled down to ground via a resistor. The FHM 3695-25 detects its master/slave configuration by monitoring the state of the TAKE pin during the startup process.

MCOT Operation - Master Phase

• Receives write and read commands from the host through the PMBus interface

• Generates the SET signal

• Manages startup, shutdown, and all protection operations

• Monitors fault alerts from slave phases via the PG pin

• Generates the first ON pulse

• Generates ON pulses when receiving RUN and SET signals

• Dynamically adjusts its on-time to ensure equal current sharing

MCOT Operation - Slave Phase

The slave phase performs the following functions:

• Receives write commands from the host through the PMBus interface

• Receives the SET signal from the master phase

• Sends OV/UV/OT fault alerts via the PG pin

• Initiates ON pulses when receiving CTRL and SET signals

• Dynamically adjusts its on-time to ensure equal current sharing based on per-phase and total current relative to its own phase

The FHM 3695-25 benefits from MCOT control, enabling extremely fast load transient response. During load transients, SET signals are generated more frequently compared to steady-state conditions. Therefore, energy is delivered to the load at a higher rate, minimizing output deviation during load transients. For the FHM 3695-25, SET pulses are generated with a minimum interval of 50ns, meaning that the next phase can be turned on as quickly as 50ns after the previous one.

Multiphase Parallel Phase Configuration

When applying the FHM3695 in a multiphase parallel configuration, phase configuration needs to be achieved by connecting a corresponding resistance value from the ADDPH pin to ground, thereby enabling phase staggering and equal current sharing.

Four-Phase Operating Timing Diagram (Steady State)

Four-Phase Operating Timing Diagram (Dynamic State)

Applications Information

Working Mode Selection

The FHM 3695-25 offers a forced CCM (Constant Current Mode) and frequency hopping working mode under light load conditions, which can be set via PMBus with commands as shown in Table 

Table 1  MFR_CTRL_OPS（D2h）

Operating Frequency

The operating frequency of the FHM 3695-25 is 600KHz.

Output Voltage Setting

The output voltage of the module can be set by the pullup resistor RTOP between VOSNS+ and VOUT, and the pulldown resistor RBOTTOM between VOSNS+ and VOSNS-. The reference calculation formula is as follows:

Soft Start

The soft start (SS) time can be programmed via PMBus. The default time is 2ms.

Pre-Bias Start-Up

The FHM 3695-25 ensures a monotonic rising start-up when the output voltage is biased. If the output voltage is pre-biased to a certain voltage during start-up, both the high-side and low-side switches will be disabled until the sensed output voltage on the VOSNS+ pin falls below the internal reference voltage.

Current Sensing and Over-Current Protection (OCP)

The FHM3695-25 features on-chip current sensing and a programmable positive current limit threshold.

The FHM 3695-25 provides two inductor valley current limits (set by register D7h).

Inductor Valley Over-Current Protection (D7h)

During the LS-FET conduction state, the inductor current is sensed and monitored on a cycle-by-cycle basis. The HS-FET is only allowed to conduct if no over-current is detected during the LS-FET conduction state. If 31 consecutive OC conditions are detected, the OCP is triggered.

In the case of an over-current condition or output short-circuit, if the output voltage falls below the Under-Voltage Protection (UVP) threshold, the FHM 3695-25 immediately enters over-current protection mode.

After triggering the OCP, whether the FHM3695-25 enters hiccup mode or latch-off mode depends on the register settings. It should be noted that once latched off, re-enabling the FHM 3695-25 requires restarting Vcc or CTRL.

The inductor valley over-current limit can be programmed via register D7h, which sets the inductor valley current limit for each phase for both single-phase and multi-phase operations. The commands are shown in Table 3.

Table3 MFR_OC_PHASE_SET（D7h）

Negative Phase Inductor Current Limit

When the current sensed by the LS-FET falls below the negative phase current limit set by register D5h[2], the device will turn off its LS-FET for a period of time to limit the load current. The period can be set via register D5h[3]. The commands are shown in Table 4.

Table4 MFR_OVP_NOCP_SET (D5h)

Over-Voltage Protection (OVP)

The FHM 3695-25 monitors the output voltage via the VOSNS+ pin at the resistor divider to detect over-voltage conditions. The over-voltage protection value can be set via register D4h, with specific commands shown in Table 5.

Table5 MFR_VOUT_OVP_FAULT_LIMIT (D4h)

Under-Voltage Protection (UVP)

The FHM 3695-25 monitors the output voltage through the VOSNS+ pin to detect under-voltage conditions. If the VOSNS+

voltage falls below the UVP threshold (set via register D9h, as shown in Table 6), the UVP is triggered. Upon triggering the UVP, the FHM 3695-25 will enter either HICCUP mode or latch-off mode, depending on the PMBus configuration. Please note that once the device is latched off, to re-enable the FHM 3695-25, a restart of Vcc or CTRL is required.

Table 6 MFR_UVP_PGOOD_ON_LIMIT (D9h)

Output Sink Mode (OSM)

When the output voltage exceeds the reference voltage by more than 5% but remains below the OVP threshold, the FHM 3695-25 enters OSM. Upon triggering OSM, the FHM 3695-25 operates in forced CCM mode. The FHM 3695-25 exits OSM mode when the HS-FET is re-activated. This feature can be enabled or disabled via register EAh[9], with instructions provided in Table 7.

Table 7 MFR_CTRL(EAh)

Over-Temperature Protection (OTP)

The FHM 3695-25 monitors the junction temperature. If the junction temperature exceeds the threshold, the converter will enter either HICCUP mode or latch-off mode, depending on the PMBus selection. Please note that once latched off, to re-enable the MPM3695-25 (assuming it's a typo for FHM 3695-25), a restart of Vcc or CTRL is required.

The junction temperature threshold can be set via register 4Fh, with specific instructions provided in Table 8. The value is unsigned, with 1 LSB equaling 1 °C, and the default value is 0x009B (155 °C).

Table 8 OT_FAULT_LIMIT (4Fh)

Power Good（PG）

The FHM 3695-25 features an open-drain signal pin for determining power good (PG) status. The PG pin can be configured as an output-only pin or as both an input and output pin via bit [0] of the MRF_CTRL_COMP (D0h) register, as shown in Instruction Table 9. For single-phase configurations, the PG pin should be configured solely as an output pin. For multi-phase operations, the PG pin should be configured as both an input and output pin to detect faults in the phases. It is necessary to pull the PG pin up to VCC or the voltage source through a pull-up resistor (typically 100kΩ).

Once input voltage is applied to the FHM 3695-25, the PG pin is pulled low. When the VOSNS+ voltage reaches the threshold set in register D9h (as shown in Instruction Table 10) and after the delay set in register D1h (as shown in Instruction Table 11), the PG pin is pulled high.

In the event of any fault, the PG pin latches low and triggers related protection functions (such as UV, OV, OT, UVLO, etc.). Once the PG pin is latched low, it cannot be pulled high again unless a new soft start is initiated.

Table 9 MFR_CTRL_COMP (D0h)

Table 10 MFR_UVP_PGOOD_ON_LIMIT (D9h)

Table 11 MFR_CTRL_VOUT (D1h)

Layout 

The layout of the PCB is crucial for the stability of the power module's operation. To achieve optimal performance, please follow these guidelines:

1. Place the input ceramic capacitors as close as possible to the VIN and PGND pins. Use large copper pours for VIN and PGND to minimize parasitic impedance and reduce thermal resistance.

2. Add VIN vias at least 3mm away from the device to minimize noise coupling caused by input pulse currents.

3. Connect AGND and PGND at a single point.

4. Place sufficient output PGND vias near the PGND pin to minimize parasitic impedance and thermal resistance.

5. Keep the ISUM trace as short as possible. In multi-phase configurations, the ISUM trace should be kept away from the VIN copper pour area. Avoid using vias as much as possible.

6. Avoid routing signal traces directly under the SW pads unless the PGND layer is used to provide shielding.

Recommended PCB Layout

Typical Applications

Typical Circuit: Single-Phase Application

Typical Circuit: Two-Phase Parallel Application

PMBUS Serial Interface

PMBus Serial Interface Explanation

The Power Management Bus (PMBus) is a two-wire, bidirectional serial interface comprising a data line (SDA) and a clock line (SCL). When the lines are "idle," they are pulled up to the bus voltage by an external source. When connected to the lines, the master device generates the

SCL signal and the device address, and orchestrates the communication sequence.

It operates based on I2C principles. The FHM 3695-25 interface serves as a PMBus slave, supporting both standard mode (100kHz) and fast modes (400kHz and 1MHz). The PMBus interface adds flexibility to power supply solutions.

Device Address

To manage multiple FHM 3695-25 devices through the same PMBus, please use the ADDR pin to program the device address for each FHM 3695-25. The ADDR pin has a current outflow of 10μA. Connect a resistor between the ADDR pin and AGND to set the ADDR voltage. The PMBus address is set by converting the pin voltage using an internal ADC. The ADDR pin can set up to 16 unique addresses. Additionally, the MFR_ADDR_PMBUS (D3h) register can be used to set the PMBus address digitally.

Once an address is selected, each device must

have a unique address during normal operation.

 Table 12 shows the relationship between ADDR resistor values and PMBus addresses.

Tbale12 PMBUS Address Setting

Table 12 PMBUS

Start and Stop Conditions

The master device initiates START/STOP signals to indicate the beginning and end of PMBus data transmission. The START condition is defined as the SDA signal transitioning from high to low while SCL is high. The STOP condition is defined as the SDA signal transitioning from low to high while SCL is high.

The master device generates the SCL clock and sends the device address and read/write direction bit R/W on the SDA line. Data is transmitted on the SDA line in 8-bit bytes. Each data byte is followed by an acknowledge bit.

PMBus Update Timing

When updating the FHM 3695-25, it requires a start condition, a valid PMBus address, a register address byte, and data bytes for a single packet update. After receiving each byte, the FHM 3695-25 acknowledges by pulling the SDA line low during the high level of a single clock pulse. A valid PMBus address selects the FHM 3695-25 for communication. The FHM 3695-25 performs the update on the falling edge of the LSB (least significant byte) byte.

Packet Error Checking (PEC)

The FHM 3695-25 PMBus interface supports the use of a Packet Error Checking (PEC) byte. The PEC byte is either sent by the FHM 3695-25 during a read operation or transmitted by the bus master to the FHM 3695-25 during a write operation.

The bus master or the FHM 3695-25 uses the PEC byte to detect errors during bus communication, depending on whether it is a read or write operation. If the master determines that the PEC byte read during a read operation is incorrect, it can decide to retry the read. If the FHM 3695-25 determines that the PEC byte sent during a write operation is incorrect, it ignores the command (does not execute it) and sets a status flag. In group commands, the master can choose to send or not send a PEC byte as part of the message to the FHM 3695-25.

PMBus Alarm Response Address (ARA)

The PMBus Alarm Response Address (ARA) is a special address that the bus master can use to locate any device that needs to communicate with it. The master typically uses hardware interrupt pins to monitor the PMBus ALERT pins of many devices. When the master is interrupted, it sends a message on the bus using PMBus receive bytes or bytes received with the PEC protocol.

The special address used by the master is 0x0C. Any device with a PMBus alert signal returns its own 7-bit address as the 7 most significant bits (MSBs) of a data byte. The least significant bit (LSB) is not used and can be either 1 or 0. The master reads the device address from the received data byte and then proceeds to handle the alert condition.

Multiple devices may have a valid PMBus alert signal and attempt to communicate with the master. In this case, the device with the lowest address takes control of the bus and successfully sends its address to the master. The successful device then disables its PMBus alert signal. If the master finds that the PMBus alert signal remains low, it will continue to read addresses until all devices that need to communicate with it have successfully sent their addresses

Instruction

OPERATION (01h)

The OPERATION is a paged register. The OPERATION command is used to turn the converter's output on/off and to control the input of the CTRL pin. It is also used to set the upper or lower limit of the output voltage. The unit remains in the commanded mode until a subsequent OPERATION command or a change in the CTRL pin state instructs the converter to switch to another mode. This OPERATION command is also used to re-enable the converter after it has been shut down due to a fault trigger. Writing an OFF command after an ON command will clear all faults. However, simply writing an ON command after a fault-triggered shutdown will not clear the fault registers. The default value is 0x80.

ON_OFF_CONFIG (02h)

The ON_OFF_CONFIG command configures the CTRL pin input and sets the combination of PMBus commands required to turn the converter on and off. The default value for this command is 0x16.

CLEAR_FAULTS (03h)

The CLEAR_FAULTS command is used to reset all stored warning and fault flags.

CAPABILITY (19h)

The CAPABILITY command returns information about the PMBus features supported by the FHM 3695-25. This command is read using the PMBus read-byte protocol. The default value for this command is 0xB0.

VOUT_MODE (20h)

The VOUT_MODE command is used to command and read the output voltage. The three most significant bits are used to determine the data format (with the FHM 3695-25 only supporting the direct format), and the remaining five bits represent the exponent used in the output voltage read/write commands. The default value for this command is 0x40.

VOUT_COMMAND (21h)

The VOUT_COMMAND sets the output voltage of the FHM 3695-25. The value is unsigned and has a resolution of 1 LSB = 2 mV. The default value for this command is 0x0258, which corresponds to 1.2V.

VOUT_MAX (24h)

The VOUT_MAX command sets the upper limit of the converter's output voltage, regardless of any other commands or combinations. The purpose of this command is to prevent users from accidentally setting the output voltage to an excessively high level that exceeds the device's maximum voltage tolerance, not just the overvoltage protection range. The value is unsigned and has a resolution of 1 LSB = 2 mV. The default value for this command is 0x0ABE, which corresponds to 5.5V.

VOUT_SCALE_LOOP (29h)

The VOUT_SCALE_LOOP sets the feedback resistor divider ratio, which is equal to VOSNS+/VOUT. Regardless of whether an external or internal feedback resistor divider is used, VOUT_SCALE_LOOP should match the actual feedback resistor divider that is being utilized. The value is unsigned and has a resolution of 1 LSB = 0.001. The default value for this command is 0x01F4, which corresponds to 0.5.

OT_FAULT_LIMIT (4Fh)

OT_FAULT_LIMIT (4Fh)

The OT_FAULT_LIMIT command is used to configure or read the threshold for over-temperature fault detection. If the measured temperature exceeds this value, over-temperature protection will be triggered. The value is unsigned and has a resolution of 1 LSB = 1°C. The default value for this command is 0x009B, which corresponds to 155°C.

OT_WARN_LIMIT (51h)

The OT_WARN_LIMIT is used to configure or read the threshold for over-temperature warning detection. The value is unsigned and has a resolution of 1 LSB = 1°C. The default value for this command is 0x0091, which corresponds to 145°C.

VIN_OV_FAULT_LIMIT (55h)

The VIN_OV_FAULT_LIMIT command is used to configure or read the threshold for input over-voltage fault detection. The value is unsigned and has a resolution of 1 LSB = 500 mV. The default value for this command is 0x0021, which corresponds to 16.5V. The set value should not exceed 18V.

VIN_OV_WARN_LIMIT (57h)

The VIN_OV_WARN_LIMIT command is used to configure or read the threshold for input over-voltage warning detection. The value is unsigned and has a resolution of 1 LSB = 500 mV. The default value for this command is 0x0021, which corresponds to 16.5V. The maximum value should not exceed 18V.

VIN_UV_WARN_LIMIT (58h)

The VIN_UV_WARN_LIMIT command is used to configure or read the threshold for input under-voltage warning detection. The value is unsigned and has a resolution of 1 LSB = 250 mV. The default value for this command is 0x0010, which corresponds to 4V. The minimum value should not be less than 3.3V.

TON_DELAY (60h)

This command is read-only, and the default value is 0x0000 (0ms).

TON_RISE (61h)

The TON_RISE command sets the soft-start time, in milliseconds, which refers to the time it takes for the output to rise from the start until the voltage reaches its regulated point. The value is unsigned, with 1 LSB = 1 ms. The default value is 0x0001 (2 ms), and the maximum value is 0x0007 (16 ms).

MFR_CTRL_VOUT (D1h)

MFR_ADDR_PMBUS (D3h)

MFR_VOUT_UV_OV_FAULT_LIMIT (D4h)

MFR_OVP_NOCP_SET (D5h)

The MFR_OVP_SET command sets the response for both output voltage OVP and input voltage OVP.

MFR_OT_OC_SET (D6h)

The MFR_OT_OC_SET command sets the response for OCP (Over-Current Protection), as well as the response and hysteresis for OTP (Over-Temperature Protection).

MFR_OC_PHASE_SET (D7h)

The MFR_OC_PHASE_LIMIT command sets the valley current limit for the inductor of each phase.

MFR_HICCUP_ITV_SET (D8h)

he MFR_HICCUP_ITV_SET command sets the HICCUP interval during OCP (Over-Current Protection) events.

MFR_UVP_PGOOD_ON_LIMIT (D9h)

MFR_FB_STEP (DAh)

MFR_LOW_POWER (E5h)

MFR_CTRL (EAh)

Package Description

RECOMMENDED LAND PATTERN

Soldering and storage precautions

Recommended reflow soldering profile

Caution:

1. Due to the large size of the module, please do not place the module under the board for reflow soldering to avoid falling off

2. For bulk products and those that have been taken out of their original packaging, they should be stored in a desiccator (with a relative humidity of less than 10% inside). For products still in their original packaging, they should also be stored in a desiccator whenever possible.

3. Before mounting on the board, it is necessary to strictly follow the baking conditions to dry the samples: bake at 125°C for more than 48 hours, and control the reflow soldering temperature within 245°